1. Field of the Invention
The present invention relates to dual-data-rate dynamic-random-access-memory (DDR-SDRAM) devices. More particularly, the present invention relates to circuits to delay the “DQS” signal from a DDR-SDRAM memory device to capture data, the “DQS” signal and the data being generated simultaneously by the memory device, the circuits including a fine delay tuning capability.
2. The Prior Art
DDR-SDRAM devices can transfer data twice as fast as single-data-rate SDRAM memory devices (SDR-SDRAM). This is because DDR-SDRAM devices can send and receive signals twice per clock cycle. This feature increases the complexity of writing data to and reading data from the DDR-SDRAM device since the valid-data window is narrower than in SDR-SDRAM devices.
Referring now to FIGS. 1A and 1B, a timing diagram illustrates the valid data time windows for SDR-SDRAM devices (FIG. 1A) and DDR-SDRAM devices (FIG. 1B) with relation to the clock timing. From FIG. 1A, it may be seen that there is a single valid data window for each complete cycle of the SDR-SDRAM clock. From FIG. 1B, it may be seen that there are two valid data windows for each DDR-SDRAM clock cycle.
In an application system, for example a microcontroller circuit connected to DDR-SDRAM devices on a printed circuit board, the signal DQS is a bidirectional control signal transmitted by the DDR-SDRAM devices during read operations and by the memory controller during write operations. The memory controller may be part of a microcontroller integrated circuit. For DDR device circuitry optimization, the DQS signal is provided edge-aligned with data for read operations and should be center-aligned with data for write operations. The DQS signal and its relationship to the valid data windows in a typical read operation, is shown in FIG. 3 and the DQS signal and its relationship to the valid data windows in a typical write operation, is shown in FIG. 2.
To write data to DDR-SDRAM devices without increasing the complexity of the DDR-SDRAM controller and to guaranty that the signal is center-aligned with data, it is possible to use the falling edge of a clock signal running at twice the frequency of the clock that drives the DDR-SDRAM devices. This aspect of operation of a DDR-SDRAM device is shown with reference to FIG. 2, in which waveforms illustrate that, for a write access from a DDR-SDRAM device, the rising and falling edges of a DDR-SDRAM DQS signal are center aligned with the valid data. The DDR-SDRAM controller generates signals with such phase relationship.
As also shown in FIG. 3, if delayed with an appropriate time increment, the delayed DQS signal is aligned with the center of the valid data window, the DQS signal can be used as a sample and hold signal which makes a simple, safe circuitry to capture data from DDR-SDRAM device.
During read operation, the DQS signal is edge-aligned with data, the controller delays the DQS signal by a period of time corresponding to about ¼ of the DDR device clock period to allow the alignment of the delayed DQS signal with the center of the valid data window. Under this condition, the data from the DDR device can be properly sampled because the hold/setup time margins are optimal (middle of data valid window, 321, 322, 331, 332). Of course, the delay must be stable.
A simple delay circuitry having DQS as its input and formed from a delay line of cascaded basic cell elements such as buffers or inverters does not guaranty a stable delay because basic element intrinsic delay depends on de-rating factors such process, voltage, and temperature variations.